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datasheet low voltage, 2.5v and 3.3v lvcmos pll clock driver mpc9600 nrnd mpc9600 revision 6 january 7, 2013 1 ?2013 integrated device technology, inc. the mpc9600 is a low voltage 2.5 v or 3.3 v compatible, 1:21 pll based clock driver and fanout buffer. with output frequencie s up to 200 mhz and output skews of 150 ps, the device meets the needs of the most demanding clock tree applications. features ? multiplication of input fr equency by 2, 3, 4, and 6 ? distribution of output frequency to 21 ou tputs organized in three output banks: qa0-qa6, qb0-qb6, qc0-qc6, each fully selectable ? fully integrated pll ? selectable output frequency range is 50 to 100 mhz and 100 to 200 mhz ? selectable input frequency range is 16.67 to 33 mhz and 25 to 50 mhz ? lvcmos outputs ? outputs disable to high impedance (except qfb) ? lvcmos or lvpecl refe rence clock options ? 48-lead qfp packaging, pb-free ? ?? 50 ps cycle-to-cycle jitter ? 150 ps maximum output-to-output skew ? 200 ps maximum static phase offset window ? nrnd ? not recommend for new designs functional description the mpc9600 is a fully lvcmos 2.5 v or 3.3 v compatible pll cl ock driver. the mpc9600 has the capability to generate clock sign als of 50 to 200 mhz from clock sources of 16.67 to 50 mhz. the in ternal pll is optimized for this frequency range and does not req uire external loop filter components. qfb provides an output for the external feedback path to the feedback input fb_in. the qfb div ider ratio is configurable and determines the pll frequ ency multiplication factor when qfb is dire ctly connected to fb_in. the mpc9600 is optimized for minimizing the propagation delay between the clock input and fb_in. three output banks of 7 outputs each bank can be individually conf igured to divide the vco frequency by 2 or by 4. combining th e feedback and output divider ratios, the mpc9600 is capabl e to multiply the input frequency by 2, 3, 4, and 6. the reference clock is selectable either l vpecl or lvcmos. the lvpecl reference clock f eature allows the desi gner to use lvpecl fanout buffers for the inner branches of the clock distribution tree. all control inputs accept lvcmos compatible levels. the o utputs provide low impedance lvcmos outputs capable of driving parallel terminated 50 ? transmission to v tt =v cc /2. for series terminated lines the mpc9600 can drive two lines per output giving the device an effe ctive total fanout of 1:42. with guaranteed maximum output-to-o utput skew of 150 ps, the mpc9600 p ll clock driver meets the synchronization requirements of the mo st demanding systems. the v cca analog power pin doubles as a pll bypass select line for test purpose. when the v cca is driven to gnd the reference clock will bypass the pll. the device is packaged in a 48-lead lqfp package to prov ide optimum combination of board density and performance. 3.3 v or 2.5 v low voltage cmos pll clock driver ae suffix 48-lead lqfp package pb-free package case 932-03 scale 2:1 nrnd ? not recommend for new designs
mpc9600 revision 6 january 7, 2013 2 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver figure 1. mpc9600 logic diagram d q (pulldown) 0 1 (pulldown) pclk ref fb 200 ? 400 mhz /2 /4 /8 /12 d q 0 1 0 1 0 1 d q 0 1 7 7 d q 0 1 oe 8 7 (pulldown) (pullup) (pullup) (pullup) (pullup) (pullup) (pulldown) pclk cclk fsela fselb fselc fsel_fb ref_sel fb_in v cca v cc gnd qb0?6 bank a qc0?6 qfb qa6 qa5 qa4 qa3 qa2 qa1 qa0 bank b bank c feedback pll v cc /2
mpc9600 revision 6 january 7, 2013 3 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver figure 2. 48-lead package pinout (top view) table 1. pin configuration ? 48 lqfp pin i/o type description pclk, pclk input pecl differential reference clock frequency input cclk input lvcmos reference clock input fb_in input lvcmos pll feedback clock input qan output lvcmos bank a outputs qbn output lvcmos bank b outputs qcn output lvcmos bank c outputs qfb output lvcmos differential feedback output ref_sel input lvcmos reference clock input select fsela input lvcmos selection of bank a output frequency fselb input lvcmos selection of bank b output frequency fselc input lvcmos selection of bank c output frequency fsel_fb input lvcmos selection of feedback frequency oe input lvcmos output enable v cca power supply analog power supply and pll bypass. an external v cc filter is recommended for v cca v cc power supply core power supply gnd ground ground gnd qa3 qa2 vcc qa1 qa0 gnd v cc qc3 qc4 gnd qc5 qc6 gnd qfb qb0 qb1 v cc qb2 qb3 gnd gnd cclk pclk pclk v cc ref_sel fsel_fb v cca 41 42 43 44 45 46 47 48 19 18 17 16 15 14 13 12345678 36 35 34 33 32 31 30 29 20 mpc9600 fb_in oe v cc fsela fselb fselc gnd 9101112 gnd qc0 qc1 qc2 23 22 21 24 qb4 qb5 qb6 v cc 28 27 26 25 v cc qa6 qa5 37 38 39 40 qa4
mpc9600 revision 6 january 7, 2013 4 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver table 2. function table (controls) control pin 0 1 ref_sel cclk pclk v cca pll bypass (1) 1. v cca = gnd, pll off and bypassed for static test and diagnosis. pll power oe outputs enabled outputs disabled (except qfb) fsela output bank a at vco/2 output bank a at vco/4 fselb output bank b at vco/2 output bank b at vco/4 fselc output bank c at vco/2 output bank c at vco/4 fsel_fb feedback output at vco/8 feedback output at vco/12 table 3. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those values beyond wh ich damage to the device may occu r. exposure to these condition s or conditions beyond those indicated may adversely affect devic e reliability. functional operati on under absolute-maximum-rated co nditions is not implied. symbol parameter min max unit v cc supply voltage ?0.3 4.6 v v in dc input voltage ?0.3 v cc + 0.3 v v out dc output voltage ?0.3 v cc + 0.3 v i in dc input current ? 20 ma i out dc output current ? 50 ma t stor storage temperature range ?65 125 ? c table 4. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc ?? 2 v mm esd protection (machine model) 400 v hbm esd protection (human body model) 4000 v cdm esd protection (charged device model) 1500 v lu latch-up immunity 200 ma c pd power dissipation capacitance 10 pf per output c in input capacitance 4.0 pf inputs
mpc9600 revision 6 january 7, 2013 5 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver table 5. dc characteristics (v cc = 3.3 v 5%, t a = ? 40c to +85c) symbol characteristics min typ max unit condition v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage 0.8 v lvcmos v pp peak-to-peak input voltage (dc) pclk, pclk 250 mv lvpecl v cmr (1) 1. v cmr (dc) is the crosspoint of the differential input signal. func tional operation is obtained when the crosspoint is within the v cmr range and the input swing lies within the v pp (dc) specification. common mode range (dc) pclk, pclk 1.0 v cc ? 0.6 v lvpecl v oh output high voltage 2.4 v i oh = ?24 ma (2) 2. the mpc9600 is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a te rmination voltage of v tt . alternatively, the device drives up to two 50 ? series terminated transmission lines. v ol output low voltage 0.55 0.30 v v i ol = 24 ma i ol = 12 ma z out output impedance 14 ? 17 w i in input leakage current ?? 150 ? a v in = v cc or gnd i cca maximum pll supply current 2.0 5.0 ma v cca pin i ccq maximum quiescent supply current 1.0 ma all v cc pins table 6. dc characteristics (v cc = 2.5 v 5%, t a = ? 40c to +85c) symbol characteristics min typ max unit condition v ih input high voltage 1.7 v cc + 0.3 v lvcmos v il input low voltage 0.7 v lvcmos v pp peak-to-peak input voltage (dc) pclk, pclk 250 mv lvpecl v cmr (1) 1. v cmr (dc) is the crosspoint of the differential input signal. func tional operation is obtained when the crosspoint is within the v cmr range and the input swing lies within the v pp (dc) specification. common mode range (dc) pclk, pclk 1.0 v cc ? 0.6 v lvpecl v oh output high voltage 1.8 v i oh = ?15 ma (2) 2. the mpc9600 is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a te rmination voltage of v tt . alternatively, the device drives up to two 50 ? series terminated transmission lines. v ol output low voltage 0.6 v i ol = 15 ma z out output impedance 17 ? 20 w i in input leakage current ?? 150 ? a v in = v cc or gnd i cca maximum pll supply current 3.0 5.0 ma v cca pin i ccq maximum quiescent supply current 1.0 ma all v cc pins
mpc9600 revision 6 january 7, 2013 6 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver table 7. ac characteristics ? 48 lqfp (v cc = 3.3 v 5% or v cc = 2.5 v 5%, t a = ?40c to +85c) (1) 1. ac characteristics are applic able over the entire ambient temperature and s upply voltage range and are production tested. ac characteristics apply for paral lel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition f ref input frequency ? 8 feedback (fsel_fb = 0) ? 12 feedback (fsel_fb = 1) static test mode (v cca = gnd) 25 16.67 0 50 33 500 mhz mhz mhz pll locked pll locked v cca = gnd f vco vco frequency 200 400 mhz f max maximum output frequency ? 2 outputs (fselx = 0) ? 4 outputs (fselx = 1) 100 50 200 100 mhz mhz pll locked pll locked f refdc reference input duty cycle 25 75 % v pp peak-to-peak input voltage pclk, pclk 500 1000 mv lvpecl v cmr (2) 2. v cmr (ac) is the crosspoint of the different ial input signal. normal ac operation is obt ained when the crosspoint is within the v cmr range and the input swing lies within the v pp (ac) specification. violation of v cmr or v pp impacts static phase offset t ( ? ). common mode range pclk, pclk (v cc = 3.3 v ?? 5%) pclk, pclk (v cc = 2.5 v ?? 5%) 1.2 1.2 v cc ?0.8 v cc ?0.6 v v lvpecl lvpecl t r , t f cclk input rise/fall time 1.0 ns see figure 11 t ( ? ) propagation delay (static phase offset) cclk to fb_in pecl_clk to fb_in ?60 +30 +40 +130 +140 +230 ps ps pll locked pll locked t sk(o) output-to-output skew all outputs, single frequency all outputs, multiple frequency within qax output bank within qbx outputs within qcx outputs 70 70 30 40 30 150 150 75 125 75 ps ps ps ps ps measured at coincident rising edge dc output duty cycle 45 50 55 % t r , t f output rise/fall time 0.1 1.0 ns see figure 11 t plz, hz output disable time 10 ns t pzl, zh output enable time 10 ns bw pll closed loop bandwidth ? 8 feedback (fsel_fb=0) ? 12 feedback (fsel_fb=1) 1.0 ? 10 0.6 ? 4.0 mhz mhz ?3 db point of pll transfer characteristic t jit(cc) cycle-to-cycle jitter (3) all outputs in ?? 2 configuration all outputs in ?? 4 configuration 40 40 130 180 ps ps refer to application section for other configurations t jit(per) period jitter (3) all outputs in ?? 2 configuration all outputs in ?? 4 configuration 3. cycle-to-cycle and period jitter depends on output divider configuration. 25 20 70 100 ps ps refer to application section for other configurations t jit( ? ) i/o phase jitter (1 ? )v cc = 3.3 v v cc = 2.5 v 17 (4) 15 (3) 4. see applications information section for max i/o phase jitter versus frequency. ps ps rms value at f vco = 400 mhz t lock maximum pll lock time 5.0 ms
mpc9600 revision 6 january 7, 2013 7 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver applications information programming the mpc9600 the mpc9600 clock driver outputs can be configured into several divider modes. additionally the external feedback of the device allows for flexibility in establishing various input to output frequency relationships. the selectable feedback divider of the three output groups allows the user to configure the device for 1:2, 1:3, 1:4 and 1:6 input:output fr equency ratios. the use of even dividers ensure that the output duty cycle is always 50%. table 8 illustrates the various output co nfigurations, the table describes the outputs using the input clock frequency clk as a reference. the feedback divider division settings establish the output relationship, in addition, it must be ensured that the vco will be stable given the frequency of the outputs desired. the feedback frequency should be used to situate the vco into a frequency range in which the pll will be stable. the design of the pll supports output frequencies from 50 mhz to 200 mhz while the vco frequency range is specified from 200 mhz to 400 mhz and should not be exceeded for stable operation. table 8. output frequency relationship (1) for qfb connected to fb_in 1. output frequency relationship with respect to input refe rence frequency clk. the vco fr equency range is always 200?400. configuration inputs input frequency range clk [mhz] output frequency ratio and range fsel_fb fsela fselb fselc ratio, qax [mhz ] ratio, qbx [mhz] ratio, qcx [mhz] 0 0 0 0 25.0?50.0 4?clk (100?200) 4?clk (100?200) 4?clk (100?200) 0 0 0 1 4?clk (100?200) 4?clk (100?200) 2?clk (50.0?100) 0 0 1 0 4?clk (100?200) 2?clk (50.0?100) 4?clk (100?200) 0 0 1 1 4?clk (100?200) 2?clk (50.0?100) 2?clk (50.0?100) 0 1 0 0 2?clk (50.0?100) 4?clk (100?200) 4?clk (100?200) 0 1 0 1 2?clk (50.0?100) 4?clk (100?200) 2?clk (50.0?100) 0 1 1 0 2?clk (50.0?100) 2?clk (50.0?100) 4?clk (100?200) 0 1 1 1 2?clk (50.0?100) 2?clk (50.0?100) 2?clk (50.0?100) 1 0 0 0 16.67?33.33 6?clk (100?200) 6?clk (100?200) 6?clk (100?200) 1 0 0 1 6?clk (100?200) 6?clk (100?200) 3?clk (50.0?100) 1 0 1 0 6?clk (100?200) 3?clk (50.0?100) 6?clk (100?200) 1 0 1 1 6?clk (100?200) 3?clk (50.0?100) 3?clk (50.0?100) 1 1 0 0 3?clk (50.0?100) 6?clk (100?200) 6?clk (100?200) 1 1 0 1 3?clk (50.0?100) 6?clk (100?200) 3?clk (50.0?100) 1 1 1 0 3?clk (50.0?100) 3?clk (50.0?100) 6?clk (100?200) 1 1 1 1 3?clk (50.0?100) 3?clk (50.0?100) 3?clk (50.0?100)
mpc9600 revision 6 january 7, 2013 8 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver figure 3. configuration for 126 mhz clocks figure 4. configuration for 133.3/66.67 mhz clocks table 9. typical and maximum period jitter specification device configuration qa0 to qa6 qb0 to qb6 qc0 to qc6 typmaxtypmaxtypmax all output banks in ?? 2 or ?? 4 divider configuration (1) ?? 2 (fsela = 0 and feslb = 0 and fselc = 0) ?? 4 (fsela = 1 and feslb = 1 and fselc = 1) 1. in this configuration, all mpc9600 out puts generate the same clock frequency. see figure 3 for an example configuration. 25 20 50 70 50 50 70 100 25 20 50 70 mixed ?? 2/ ?? 4 divider configurations (2) for output banks in ?? 2 divider configurations for output banks in ?? 4 divider configurations 2. multiple frequency generation. jitter data are sp ecified for each output divider separately. see figure 7 for an example. 80 25 130 70 100 60 150 100 80 25 130 70 table 10. typical and maximum cycle-to-cycle jitter specification device configuration qa0 to qa6 qb0 to qb6 qc0 to qc6 typmaxtypmaxtypmax all output banks in ?? 2 or ?? 4 divider configuration (1) ?? 2 (fsela = 0 and feslb = 0 and fselc = 0) ?? 4 (fsela = 1 and feslb = 1 and fselc = 1) 1. in this configuration, all mpc9600 outputs generate the same clock frequency. 40 40 90 110 80 120 130 180 40 40 90 110 mixed ? 2/ ? 4 divider configurations (2) for output banks in ? 2 divider configurations for output banks in ? 4 divider configurations 2. multiple frequency generation. jitter data are specified for each output divider separately. 150 30 250 110 200 120 280 180 150 30 250 110 mpc9600 f ref = 20.833 mhz 125 mhz 125 mhz 20.833 mhz (feedback) 125 mhz cclk fb_in fsel_fb fsela fselb fselc qa0?6 qb0?6 qc0?6 qfb 7 7 7 1 0 0 0 frequency range min max input 16.67 mhz 33.33 mhz qa outputs 100 mhz 200 mhz qb outputs 100 mhz 200 mhz qc outputs 100 mhz 200 mhz frequency range min max input 25 mhz 50 mhz qa outputs 100 mhz 200 mhz qb outputs 100 mhz 200 mhz qc outputs 100 mhz 200 mhz mpc9600 f ref = 33.33 mhz 133.3 mhz 66.67 mhz 33.33 mhz (feedback) 66.67 mhz cclk fb_in fsel_fb fsela fselb fselc qa0?6 qb0?6 qc0?6 qfb 7 7 7 0 0 1 1
mpc9600 revision 6 january 7, 2013 9 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver power supply filtering the mpc9600 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. random noise on the v cca (pll) power supply impacts the device characteristics, for instance i/o jitter. the mpc9600 provides separate power supplies for the output buffers (v cc ) and the phase-locked loop (v cca ) of the device.the purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal an alog phase-locked loop . in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simple but effective form of isolatio n is a power supply filter on the v cca pin for the mpc9600. figure 5 illustrates a typical power supply filter scheme. the mpc9600 frequency and phase stability is most susceptible to noise with spectral content in the 100 khz to 20 mhz range. therefore the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop across the series filter resistor r f . from the data sheet the i cca current (the current sourced through the v cca pin) is typically 3 ma (5 ma maximum), assuming that a minimum of 2.325 v (v cc =3.3v or v cc =2.5 v) must be maintained on the v cca pin. the resistor r f shown in figure 5 , must have a resistance of 9 ? 10 ? (v cc = 2.5 v) to meet the voltage drop criteria. the minimum values for r f and the filter capacitor c f are defined by the required filter characteristics: the rc filter should provide an attenuation greater than 40 db for noise whose spectral content is above 100 khz. in the example rc filter shown in figure 5 , the filter cut-off frequency is around 3-5 khz and the noise attenuation at 100 khz is better than 42 db. figure 5. v cca power supply filter as the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. although the mpc9600 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll) there still may be applications in which overall performance is being degraded due to system power supply noise. th e power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. using the mpc9600 in zero-delay applications nested clock trees are typical applications for the mpc9600. for these applic ations the mpc9600 offers a differential lvpecl clock input pair as a pll reference. this allows for the use of differential lvpecl primary clock distribution devices such as the freescale semiconductor mc100es6111 or mc100es6226, taking advantage of its superior low-skew performance. clock trees using lvpecl for clock distribution and the mpc9600 as lvcmos pll fanout buffer with zero insertion delay will show significantly lower clock skew t han clock distributions developed from cmos fanout buffers. the external feedback option of the mpc9600 pll allows for its use as a zero delay buffer. the pll aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. the remaining insertion delay (skew error) of the mpc9600 in zero-delay applications is measured between the reference clock input and any output. this effectiv e delay consists of the static phase offset (spo or t ( ? ) ), i/o jitter (t jit( ? ) , phase or long-term jitter), feedback path delay and the output-to-output skew (t sk(o) ) relative to the feedback output. calculation of part-to-part skew the mpc9600 zero delay buffer supports applications where critical clock signal timing c an be maintained across several devices. if the reference clock inputs (cclk or pclk) of two or more mpc9600 are connected together, the maximum overall timing uncertainty from the common cclk input to any output is: t sk(pp) = t ( ? ) + t sk(o) + t pd, line(fb) + t jit( ? ) ? cf this maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and i/o (phase) jitter: figure 6. mpc9600 maximum device-to-device skew v cca v cc mpc9600 10 nf c f r f v cc 33...100 nf r f = 9?10 ? for v cc = 2.5 v or v cc = 3.3 v c f = 22 ? f for v cc = 2.5 v or v cc = 3.3 v t pd,line(fb) t jit( ? ) +t sk(o) ?t ( ? ) +t ( ? ) t jit( ? ) +t sk(o) t sk(pp) max. skew tclk common qfb device 1 any q device 1 qfb device2 any q device 2
mpc9600 revision 6 january 7, 2013 10 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver due to the statistical nature of i/o jitter a rms value (1 ? ) is specified. i/o jitter numbers for other confidence factors (cf) can be derived from ta b l e 11 . the feedback trace delay is de termined by the board layout and can be used to fine-tune the effective delay through each device. in the following example calculation a i/o jitter confidence factor of 99.7% ( ? 3 ? ) is assumed, resulting in a worst case timing uncertainty from input to any output of ? 261 ps to 341 ps relative to cclk (v cc = 3.3 v and f vco = 200 mhz): t sk(pp) = [?60 ps...140 ps] + [?150 ps...150 ps] + [(17 ps @ ?3)...(17 ps @ 3)] + t pd, line(fb) t sk(pp) = [?261 ps...341 ps] + t pd, line(fb) above equation uses the maximum i/o jitter number shown in the ac characteristic table for v cc = 3.3 v (17 ps rms). i/o jitter is frequency dependant with a maximum at the lowest vco frequency (200 mhz for the mpc9600). applications using a higher vco frequency exhibit less i/o jitter than the ac characteristic limit. the i/o jitter characteristics in figure 7 can be used to derive a smaller i/o jitter number at the specific vco frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew t sk(pp) . figure 7. i/o jitter versus vco frequency for v cc = 2.5 v and v cc = 3.3 v driving transmission lines the mpc9600 clock driver was designed to drive high speed signals in a terminated transmi ssion line environment. to provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of less than 20 ? the drivers can drive either parallel or series terminated transmission lines. for more information on transmission lines the reader is referred to freescale semiconductor application note an1091. in most high performance clock networks point-to-point distribution of signals is the method of choice. in a poin t-to-point scheme either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 ? resistance to v cc ? 2. this technique draws a fairly hi gh level of dc current and thus only a single terminated line can be driven by each output of the mpc9600 clock driver. for the series terminated case however there is no dc current draw, thus the outputs can drive multiple series terminated lines. figure 8 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. when taken to its extreme the fanout of the mpc9600 clock driver is effectively doubled due to its capability to drive multiple lines. figure 8. single versus dual transmission lines the waveform plots in figure 9 shows the simulation results of an output driving a single line versus two lines. in both cases the drive capability of the mpc9600 output buffer is more than sufficient to drive 50 ? transmission lines on the incident edge. note from the delay measurements in the simulations a delta of only 43 ps exists between the tw o differently loaded outputs. this suggests that the dual line drivi ng need not be used exclusively to maintain the tight output-to-output skew of the mpc9600. the output waveform in figure 9 shows a step in t he waveform, this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 36 ? series resistor plus the output impedance does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: v l =v s (z 0 ? (r s + r 0 + z 0 )) z 0 =50 ? || 50 ? r s =36 ? || 36 ? r 0 =14 ? v l = 3.0 (25 ? (18 + 17 + 25) =1.31 v table 11. confidence factor cf cf probability of clock edge within the distribution ? 1 ? 0.68268948 ? 2 ? 0.95449988 ? 3 ? 0.99730007 ? 4 ? 0.99993663 ? 5 ? 0.99999943 ? 6 ? 0.99999999 18 16 14 12 10 8 6 4 2 0 200 220 240 260 280 300 320 340 360 380 400 vco frequency (mhz) v cc = 3.3 v v cc = 2.5 v maximum i/o jitter versus frequency tjit(?) [ps] rms 14 ? in mpc9600 output buffer r s = 36 ? z o = 50 ? outa 14 ? in mpc9600 output buffer r s = 36 ? z o = 50 ? outb0 r s = 36 ? z o = 50 ? outb1
mpc9600 revision 6 january 7, 2013 11 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver at the load end the voltage will double due to the near unity reflection coefficient, to 2.6 v. it will then increment towards the quiescent 3.0 v in steps separated by one round trip delay (in this case 4.0 ns). figure 9. single versus dual waveforms since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted refl ections on the line. to better match the impedances when driving multiple lines the situation in figure 10 should be used. in this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. figure 10. optimized dual line termination the following figures illustrate the measurement reference for the mpc9600 clock driver circuit. figure 11. cclk mpc9600 ac test reference figure 12. pclk mpc9600 ac test reference voltage (v) outb t d = 3.9386 outa t d = 3.8956 in 2 4 6 8 10 12 14 time (ns) 3.0 2.5 2.0 1.5 1.0 0.5 0 z o = 50 ? z o = 50 ? 14 ? mpc9600 output buffer r s = 22 ? r s = 22 ? 14 ? + 22 ? || 22 ? = 50 ? || 50 ? 25 ?? = 25 ? pulse generator z = 50 ?? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? mpc9600 dut v tt v tt differential pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ?? z o = 50 ?? mpc9600 dut v tt v tt
mpc9600 revision 6 january 7, 2013 12 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver figure 14. propagation delay (t ? , status phase offset) test reference figure 16. output duty cycle (dc) figure 18. cycle-to-cycle jitter figure 19. period jitter figure 21. transition time test reference t p the time from the pll controlled edge to the non controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc v cc ?? 2 gnd t 0 dc = t p /t 0 x 100% the variation in cycle time of a signa l between adjacent cycles, over a random sample of adjacent cycle pairs t n t jit(cc) = | t n ?t n+1 | t n+1 the deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles t jit(p) = | t n ?1 / f 0 | t 0 t f t r v cc = 3.3 v 2.4 0.55 v cc v cc ?? 2 gnd t ( ? ) pclk fb_in pclk v pp v cmr t ( ? ) v cc v cc ?? 2 gnd v cc v cc ?? 2 gnd tclk fb_in figure 15. propagation delay (t ? ) test reference the pin-to-pin skew is defined as the wo rst case difference in propagation delay between any similar delay pa th within a single device v cc v cc ?? 2 gnd v cc v cc ?? 2 gnd t sk(o) figure 17. output-to-output skew t sk(o) t jit( ? ) = | t 0 ?t 1 mean | cclk fb_in the deviation in t 0 for a controlled edge with respect to a t 0 mean in a random sample of cycles (pclk) figure 20. i/o jitter v cc = 2.5 v 1.8 0.6
case 932-03 issue f 48-lead lqfp package notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. dimensioning and tolerancing per asme y14.5m, 1994. controlling dimension: millimeter. datum plan ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. datums t, u, and z to be determined at dataum plane ab. dimensions s and v to be determined at seating plane ac. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350. minimum solder plate thickness shall be 0.0076. exact shape of each corner is optional. a a1 z 0.200 ab t-u 4x z 0.200 ac t-u 4x b b1 1 12 13 24 25 36 37 48 s1 s v v1 detail y 9 t u z p ae ae t, u, z detail y m? top & bottom l? w k aa e c h 0.250 r detail ad gauge plane ad g 0.080 ac ab ac base metal n j f d t- u m 0.080 z ac section ae-ae min 1.400 0.170 1.350 0.170 0.050 0.090 0.500 0.090 0? 0.150 max 1.600 0.270 1.450 0.230 0.150 0.200 0.700 0.160 7? 0.250 dim a a1 b b1 c d e f g h j k m n p l r s s1 v v1 w aa millimeters 7.000 bsc 3.500 bsc 7.000 bsc 3.500 bsc 0.500 bsc 12? ref 0.250 bsc 9.000 bsc 4.500 bsc 9.000 bsc 4.500 bsc 0.200 ref 1.000 ref package dimensions mpc9600 revision 6 january 7, 2013 13 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver
mpc9600 revision 6 january 7, 2013 14 ?2013 integrated device technology, inc. mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver revision history sheet rev table page description of change date 6 1 nrnd ? not recommend for new designs 1/7/13
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution mpc9600 data sheet low voltage, 2.5v and 3.3v lvcmos pll clock driver

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